1. Field of the Invention
The present invention relates to a wafer level chip size package (WLCSP) and a method of manufacturing the same.
2. Description of the Related Art
A desire to make electronic products small, light, and have high performance develops into a desire to make electronic parts small, light, and have high performance. Such a desire causes development in various packaging technologies with development in technologies of designing and manufacturing semiconductors. The representative examples of the packaging technologies are ball grid array (BGA), flip-chip, and chip size package (CSP) based on area array and a surface-mount packaging. Among the above, the CSP is a packaging technology spotlighted by enabling a small package having a size the same as a real chip size to be developed. In particular, in a wafer level chip size package (WLCSP), the packaging is performed in a wafer level so that packaging costs per a chip can be remarkably reduced.
The WLCSP includes a redistribution layer (RDL) wiring traces, an under bump metallurgy (UBM) layer forming a bump, and a passivation layer protecting a circuit.
In the WLCSP, since only the RDL layer is actually used to form a circuit, when it is necessary to constitute a complicated circuit, two or more RDL layers are required. Therefore, since the number of passivation layers is to be increased, the packaging becomes very complicated and manufacturing costs increase.